Equalizer for an Integrated Optical Receiver in 65nm Cmos

This book describes the design of an analog equalizer for a fully integrated optical receiver in 65nm CMOS process which compensates for the limited bandwidth of n-well/p-sub photodiode with a roll-down of about 5dB/decade. A transimpedance amplifier which has a transimpedance gain of 70dB? and 3dB bandwidth of 1.3GHz is also designed in this work. Equalization extends the bandwidth of the optical receiver to 1GHz from 6MHz. The design is simulated with Cadence Spectre simulator. Corner simulations are performed to ensure robust operation under process variations. Total power consumption is 7mW.